Following dramatical development of electronics industry, there is increased requirement of high density and high performance, and a demand therefor is greatly increased also with respect to printed circuit boards. Among them, in regard to manufacturing technology for multi-layered Printed Circuit Boards (PCBs), various devices for realization of high density are made.
Particularly, in manufacturing process for PCBs, a build-up process using copper as wiring material and using via hole as interlayer connection is focused at present.
The build-up process is directed to a method for manufacturing PCBs which comprises alternately laminating conductive layers and insulating layers, and performing interlayer connection by via therebetween. This build-up process is a method for filling inside of the via by metal using electro-plating for the purpose of staking via of upper layer via on via with a view to realization of high density of wiring.
At present, as the build-up process using electro-plating, the semi-additive process and the full-additive process are used many times.
A cross sectional view of a printed circuit board formed by the semi-additive process is shown in FIG. 3. This semi-additive process is directed to a method for applying catalyst onto a substrate where via hole 47 is formed, forming an electroless plating film 44 as an underlying part for electric conduction of electro-plating, and performing embedding of the via hole 47 and formation of electro-plating film 46 as a wiring pattern by the electro-plating with plating resist 45 for allowing a part serving as the wiring pattern to be exposed being as mask.
In addition, a cross sectional view of a printed circuit board formed by the full-additive process is shown in FIG. 4. This full-additive process is directed to a method for applying catalyst onto a substrate where via hole 54 is formed, allowing a part serving as the wiring pattern to be exposed by plating resist 55, and performing formation of a circuit including electroless plating film 56 only by electroless copper plating.
Non-Patent Literature 1:
“Uniform Precipitation Characteristic of Electroless Copper Plating onto Fine Via Hole” by Shinji Abe, Tomoyuki Fujinami, Takayuki Seino & Hideo Honma, Association of Surface Technology Vol. 148 No. 4. p433-438. (1997)
Patent Literature 1: Japanese Patent Application No. 1992-3676
Patent Literature 2: Japanese Patent Application Laid Open No. 1993-335713